Nvidia Vera CPU: 88 Olympus Cores Built for Agentic AI Workloads

What Nvidia's Vera CPU Is Designed to Do

Vera is the CPU half of Nvidia's Vera Rubin platform, and the company has now filled in the architectural picture around it. The chip uses an Arm-based design with a fully custom core Nvidia calls Olympus, and the target workload is unusually specific: agentic AI. That means complex reasoning, tool execution, code generation, and task planning — the CPU-heavy work that sits around and between model inference rather than inside it.

Nvidia hasn't positioned Vera as a single-purpose accelerator companion, though. The chip is pitched as a general-purpose data center processor that also handles scientific data processing and reinforcement learning, both of which lean harder on CPU throughput than a typical AI serving workload does. Alongside the architectural disclosure, Nvidia is claiming higher single-core performance than competing server parts — a notable line to draw given how much of the data center CPU conversation has centered on core counts rather than per-thread speed.

Inside the Olympus Core Architecture

Each Vera CPU carries 88 Olympus cores and 176 physical threads on a monolithic compute die. Nvidia describes the core in three parts: a wide front-end with optimized branch predictors, a mid-core section built around critical path acceleration, and an execution engine tuned for complex vector operations.

Front-End: Instruction Fetch, Decode, and Branch Prediction

The front-end is where Nvidia has spent the most visible effort. Olympus supports high-bandwidth instruction fetch of up to 16 instructions per cycle, feeding a 10-wide decode engine that can process up to ten fused instructions per cycle. A 48-instruction decode queue sits behind that pipeline, and each core includes a 64KB four-way L1 instruction cache.

Branch prediction gets its own headline feature. The Olympus branch prediction subsystem includes a neural branch predictor that reduces wrong-path execution on certain branch patterns. Paired with the wide decode path, Nvidia says this lifts front-end throughput specifically for latency-sensitive work — the agentic AI and reinforcement learning cases the chip was built around, where branchy control flow tends to punish narrower designs.

Mid-Core, Cache Hierarchy, and Data Prefetch

The mid-core carries a 96KB six-way L1 data cache and a 2MB eight-way L2 cache. Above that, the die provides 164MB of unified L3 shared across the core complex.

Nvidia has also included a hardware graph prefetcher aimed at graph and analytics workloads, where memory access patterns are irregular enough that conventional stride-based prefetching struggles. That inclusion says something about the intended deployment: this is a chip expected to run pointer-chasing analytics as well as agent orchestration.

Spatial Multithreading and On-Die Bandwidth

Olympus integrates Nvidia's Spatial Multithreading technology, which allows flexible partitioning of core resources rather than fixed allocation between threads. In a design running 176 threads across 88 cores, how those resources get divided matters as much as the raw thread count.

Tying the cores together is the Scalable Coherency Fabric, which delivers 3.4 TB/s of on-die core-to-core bandwidth. That figure is the one to watch for anyone evaluating Vera for tightly coupled parallel work, since core-to-core communication is a common ceiling on scaling once core counts climb into the high double digits.

Memory Capacity, I/O, and Dual-Socket Scaling

On the memory side, Vera pairs with SOCAMM2 LPDDR5X for 1.2 TB/s of aggregate bandwidth and supports up to 1.5 TB of capacity per CPU. The use of LPDDR5X rather than conventional server DIMMs is consistent with Nvidia's broader platform strategy, trading some configurability for bandwidth and power efficiency.

Connectivity covers NVLink-C2C at 1.8 TB/s, PCIe 6.4, and CXL 3.1. Vera also scales to dual-socket configurations, with each socket exposing 176 PCIe Gen 6 lanes.

Dual-socket systems normally introduce latency headaches through NUMA fragmentation, and Nvidia is addressing that in software rather than silicon: each socket presents itself as a single NUMA domain, which avoids fragmentation and produces a clean two-NUMA-node topology for the operating system and scheduler to work with. For workloads that are sensitive to memory locality — and agentic pipelines with large working sets often are — a predictable topology can matter more than peak interconnect numbers.

The Performance Claim Against AMD Epyc Turin

Nvidia has backed its performance messaging with internal SPEC CPU 2026 results run earlier this month. The published data indicates Vera reaching up to 1.8 times the performance of AMD Epyc Turin 9755 systems in selected agentic AI workloads, including the 714.cpython_r test.

Two caveats are worth holding onto. The first is that these are vendor-supplied numbers that have not been independently verified. The second is the word "select" — a 1.8x figure drawn from specific benchmark components in a suite is not a claim about general-purpose throughput across the whole workload spectrum. Independent testing on shipping silicon will determine how much of that margin survives contact with production environments.