AMD is doing something unusual with its upcoming Zen 6 processors. Instead of designing a new low-power core around a single architecture, the company appears to be assembling one from pieces of several earlier Zen designs. The details surfaced in a recent Linux kernel patch that shows how the system identifies and manages these cores.

What the Linux kernel patch reveals

The patch treats the low-power cores as their own category rather than grouping them with AMD's existing compact "C" cores. That's a meaningful distinction — the cores are different enough to warrant separate classification instead of being folded into an existing bucket.

It also points to a practical gap. These cores currently show up as "unknown" in the CPU topology, so the system needs a proper way to identify them in user space. The patch addresses scaling behavior too: on supported AMD and Hygon chips, the cores should scale performance using amd_get_highest_perf() rather than the fixed CPPC_HIGHEST_PERF_PERFORMANCE limit. That brings them in line with how existing efficiency cores are already managed.

Five Zen generations inside one core

The construction is what makes this design stand out. Analysis from leaker InstLatX64 points to a hybrid built from multiple generations of Zen, with each major component pulled from a different era:

 

Component

 

 

Generation

 

 

Instruction set

 

 

Zen 6

 

 

Microarchitecture

 

 

Zen 5

 

 

Floating-point unit

 

 

Zen 4

 

 

L2 cache

 

 

Zen 3

 

 

L3 cache

 

 

Zen 2

 

So rather than starting from a blank sheet, AMD looks to be reusing and recombining components it already has. That mix-and-match approach suggests the goal is better efficiency without the development time and complexity that a ground-up design would demand.

How the low-power cores fit into a three-tier lineup

These cores would sit alongside AMD's current Performance and Efficiency cores, creating a three-tier structure:

  • Performance cores handle high-clock workloads.
  • Efficiency cores are smaller and tuned for lower power use.
  • Low-power cores go further still, targeting very light workloads where minimizing power draw is the whole point.

In purpose, that puts them closer to Intel's low-power efficiency cores, though AMD's design is structured differently.

Why this matters most on laptops and handhelds

The clearest payoff is in mobile devices. Laptops and gaming handhelds could push lighter tasks onto the low-power cores and cut overall power consumption in the process. That could extend battery life and allow certain processes to run at just a few watts.

The catch is scheduling. How much of a difference this actually makes depends heavily on how well software can manage and assign workloads across three different core types. Hardware alone doesn't deliver the benefit.

What AMD hasn't shared yet

There are real gaps in what's known. AMD hasn't released performance or efficiency figures for these cores, and it isn't clear how well a blended architecture will scale under real workloads. The design is unconventional, and whether it succeeds will likely come down to how smoothly the hardware and software layers work together.

Market conditions that could slow adoption

The timing adds another layer of uncertainty. AMD is currently rolling out its Zen 6 server chips, with desktop versions expected later this year. The broader market, though, isn't especially cooperative. PC shipments have been trending down, and higher memory prices — driven in part by AI demand — are pushing system costs up.

That's a bigger obstacle in laptops and handhelds than elsewhere. In those devices, upgrading the CPU generally means replacing the whole machine. Even if AMD delivers a genuine efficiency win, it may not reach many people if buyers decide to hold off on new hardware.

A shift in how AMD approaches core design

Building a core from a mix of proven parts is a notable change in direction. Instead of stretching one architecture to cover every use case, AMD is carving out more specialized roles for different core types. If the approach holds up, it could give the company more flexibility in designing chips for power-sensitive devices.